A computing device may include a Peripheral Component Interconnect (PCI) or a PCI express (PCIe), to connect between components of a motherboard, e.g., a host bridge and/or a Central Processing Unit (CPU), and one or more peripheral components of the device, e.g., a graphics card, a sound card, externally connected hardware, or the like. The PCI may transfer to the host bridge a Message Signaled Interrupt (MSI) request generated by a peripheral component. The MSI request includes a request to interrupt one or more ongoing operations of the CPU, in order to prioritize the execution of a sequence of operations related to the peripheral component. A MSI request may include a notification in the form of a write transaction that includes identification data of the message, e.g., a data field, an address field, and additional data defining the interrupt request. Based on the identification data, the host bridge receiving the MSI request may determine characteristics of the MSI request, for example, a source component and a type of the MSI request. The host bridge may send portions of the identification data to the CPU, which processes the interrupt request.
The host bridge may receive a large number of MSI requests from one or more peripheral components during a short period of time. Therefore, the host bridge may be incapable of managing all MSI requests and sending the requests to the CPU in a time-efficient manner, causing accumulation of data of un-processed requests in a memory of the host bridge.
Some computing devices store a certain number of MSI requests in the memory of the host bridge; however, this memory is generally limited and insufficient for storing a large number of MSI requests. In other computing devices, an incoming MSI request may be mapped to a value, stored in a-bit vector of pre-defined size. Based on the mapped value of the MSI request, an interrupt bit is sent to the CPU, for the CPU to manage the MSI request accordingly. This, however, may limit the managing of various types of MSI requests originating in a single peripheral component, since there exists only one value representing each specific peripheral component. In other computing devices, for example, an application associated with the CPU may define a FIFO structure of pre-set size in a memory of the host bridge, and may store data of each MSI request in an entry of the FIFO structure; however, this may cause a situation in which stored unprocessed MSI requests overflow.